Electrical failures of data lines in lower layers of an integrated circuit (IC) can be difficult to isolate and characterize. One technique for examining such failures involves removing layers from the surface of the IC until the layer of interest is exposed, followed by electrical probing data lines on that layer. Typically, accessing the structure of interest is done by mechanical polishing or milling until the layer is reached and the failure is electrically isolated. As such, this technique is not suited to isolate failures that extend over more than one layer of the IC. Further, such a technique only allows a small segment of a data line to be exposed and inspected and thus is not suitable for longer data lines.
Another technique involves cutting a cross-section or “lamella” of the IC device and analyzing the lamella with a scanning transmission electron microscope (STEM) detector. This technique, however, requires additional steps of removing a sample of the IC from the bulk material before characterizing the data lines in the sample. Further, since this technique takes a sample of the IC, it is not suitable for characterizing longer data lines that extend across the IC.
Accordingly, there exists a need in the art for methods and apparatus for electrically characterizing long data lines in an IC that overcome the aforementioned disadvantages.